1. Technical Field
Example embodiments relate generally to a soft-start circuit and a power management integrated circuit device, and, more particularly, to an integrated circuit which supports a soft-start scanning test in an initial stage for restraining inrush current when a DC-DC converter initializes.
2. Description of the Related Art
In recent years, as mobile apparatus such as smart phones, tablet computers, and the like, continue to become increasingly popular, the demand for effective power management in such devices continues to increase. Accordingly, Power Management Integrated Circuit Devices (PMIC), responsible for managing power in mobile devices, are receiving attention.
At the same time, as the display panels of mobile devices become larger in size and produce images at high-definition resolutions, power consumption is increased, and available battery time of the smart phone is reduced. Thus, the reduction of power consumption and increase of power efficiency are key factors in PMIC design.
Since the mobile display panel requires a power source having a high driving voltage and high power efficiency, an analog regulator such as a conventional low dropout regulator may not be used, so it has become common to employ a charge pump or a step-up/down inverting/non-inverting DC-DC converter.
In the case of a converter, such as a DC-DC converter using a high-capacitance filter capacitor, if an output voltage is increased at a rapid speed during an initial start-up operation, an inrush current, which is greater than a reference current by several tens of times, may flow therethrough to charge the filter capacitor in a relatively short time period. Thus, the initial inrush current must be suitably controlled to prevent the inner blocks of the integrated circuit from receiving stress by limiting the current or the voltage using a soft-start scheme.
Although the conventional soft-start can be simply implemented by using the charge and discharge of the capacitor, a predictable soft-start time characteristic may not be achieved when the soft-start time is controlled for a long time (>1 ms) or when a target output voltage is changed. Further, in the case of the charge and discharge of the capacitor, although a ramp-up soft-start is possible, the timing control for the soft start is very difficult in the case of the ramp-down due to the natural discharge characteristics of the capacitor.
In other schemes, if the soft-start time characteristics are controlled using a clock, the soft-start time control can be achieved for a relatively long time. However, since an internal reference clock is used, the number of counter bits must be increased when the time for the timing control is needed to be lengthened, so the chip size may be enlarged or current consumption may be increased by virtue of the large counter size.